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*/
#ifndef __S3C2440_SOC_H
#define __S3C2440_SOC_H
#define __REG(x) (*(volatile unsigned int *)(x))
/*Memory Controllers*/
#define BWSCON __REG(0x48000000) //Bus width & wait status control
#define BANKCON0 __REG(0x48000004) //Boot ROM control
#define BANKCON1 __REG(0x48000008) //BANK1 control
#define BANKCON2 __REG(0x4800000C) //BANK2 control
#define BANKCON3 __REG(0x48000010) //BANK3 control
#define BANKCON4 __REG(0x48000014) //BANK4 control
#define BANKCON5 __REG(0x48000018) //BANK5 control
#define BANKCON6 __REG(0x4800001C) //BANK6 control
#define BANKCON7 __REG(0x48000020) //BANK7 control
#define REFRESH __REG(0x48000024) //DRAM/SDRAM refresh control
#define BANKSIZE __REG(0x48000028) //Flexible bank size
#define MRSRB6 __REG(0x4800002C) //Mode register set for SDRAM BANK6
#define MRSRB7 __REG(0x48000030) //Mode register set for SDRAM BANK7
/*USB Host Controller*/
#define HcRevision __REG(0x49000000)
#define HcControl __REG(0x49000004)
#define HcCommonStatus __REG(0x49000008)
#define HcInterruptStatus __REG(0x4900000C)
#define HcInterruptEnable __REG(0x49000010)
#define HcInterruptDisable __REG(0x49000014)
#define HcHCCA __REG(0x49000018)
#define HcPeriodCuttentED __REG(0x4900001C)
#define HcControlHeadED __REG(0x49000020)
#define HcControlCurrentED __REG(0x49000024)
#define HcBulkHeadED __REG(0x49000028)
#define HcBulkCurrentED __REG(0x4900002C)
#define HcDoneHead __REG(0x49000030)
#define HcRmInterval __REG(0x49000034)
#define HcFmRemaining __REG(0x49000038)
#define HcFmNumber __REG(0x4900003C)
#define HcPeriodicStart __REG(0x49000040)
#define HcLSThreshold __REG(0x49000044)
#define HcRhDescriptorA __REG(0x49000048)
#define HcRhDescriptorB __REG(0x4900004C)
#define HcRhStatus __REG(0x49000050)
#define HcRhPortStatus1 __REG(0x49000054)
#define HcRhPortStatus2 __REG(0x49000058)
/*Interrupt Controller*/
#define SRCPND __REG(0X4A000000) //Interrupt request status
#define INTMOD __REG(0X4A000004) //Interrupt mode control
#define INTMSK __REG(0X4A000008) //Interrupt mask control
#define PRIORITY __REG(0X4A00000C) //IRQ priority control
#define INTPND __REG(0X4A000010) //Interrupt request status
#define INTOFFSET __REG(0X4A000014) //Interrupt request source offset
#define SUBSRCPND __REG(0X4A000018) //Sub source pending
#define INTSUBMSK __REG(0X4A00001C) //Interrupt sub mask
/*DMA*/
#define DISRC0 __REG(0x4B000000) //DMA 0 initial source
#define DISRCC0 __REG(0x4B000004) //DMA 0 initial source control
#define DIDST0 __REG(0x4B000008) //DMA 0 initial destination
#define DIDSTC0 __REG(0x4B00000C) //DMA 0 initial destination control
#define DCON0 __REG(0x4B000010) //DMA 0 control
#define DSTAT0 __REG(0x4B000014) //DMA 0 count
#define DCSRC0 __REG(0x4B000018) //DMA 0 current source
#define DCDST0 __REG(0x4B00001C) //DMA 0 current destination
#define DMASKTRIG0 __REG(0x4B000020) //DMA 0 mask trigger
#define DISRC1 __REG(0x4B000040) //DMA 1 initial source
#define DISRCC1 __REG(0x4B000044) //DMA 1 initial source control
#define DIDST1 __REG(0x4B000048) //DMA 1 initial destination
#define DIDSTC1 __REG(0x4B00004C) //DMA 1 initial destination control
#define DCON1 __REG(0x4B000050) //DMA 1 control
#define DSTAT1 __REG(0x4B000054) //DMA 1 count
#define DCSRC1 __REG(0x4B000058) //DMA 1 current source
#define DCDST1 __REG(0x4B00005C) //DMA 1 current destination
#define DMASKTRIG1 __REG(0x4B000060) //DMA 1 mask trigger