AD4052数据手册和产品信息

发布时间: 2024-11-11 09:18:00
来源: analog.com
AD4052 Functional Block Diagram
AD4052 Pin Configuration
AD4052/AD4058 Pin Configuration
AD4052 Circuit Diagram
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特性
  • Small footprint, big performance
    • INL: ±0.5 LSB maximum
    • SNR: 86.1 dB with V REF = 3.3 V
    • 1.35 mW at 1 MSPS in Sample Mode
    • 370 μW at 1 MSPS in Autonomous Modes
    • 4.1 μW standby power
  • Versatile signal conditioning integration
    • Easy Drive features enable small, low-power analog front end designs
    • Compatible with differential and single-ended signal chains
    • Wide common-mode input range
  • Minimizes digital host activity and power dissipation
    • Autonomous sampling with window comparator and interrupt generation
    • Averaging filter with continuous and burst sampling options
    • Power cycling synchronization for companion devices
  • 4-wire SPI compatible with 1.8 V to 3.3 V logic
  • 2.0 mm × 2.6 mm LFCSP and 1.7 mm × 2.0 mm WLCSP
  • Wide operating temperature range: −40°C to +125°C
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The AD4052/AD4058 areversatile, 16-bit, successive approximation register (SAR) analog-to-digital converter (ADC) that enables low-power, high-density data acquisition solutions without sacrificing precision. This ADC offers a unique balance of performance and power efficiency, plus innovative features for seamlessly switching between high-resolution and low-power modes tailored to the immediate needs of the system. The AD4052/AD4058 are ideal for battery-powered, compact data acquisition and edge sensing applications.

The Easy Drive features enable highly efficient analog front end (AFE) designs. The small sampling capacitors (3.4 pF) maximize input impedance, thus reducing the dependence on high-bandwidth, power-hungry amplifiers typically required by SAR ADCs. The wide input common-mode range grants inherent support for both differential and single-ended signals.

The AD4052/AD4058 support microcontrollers with power-down modes and interrupt-driven firmware. The autonomous modes enable out-of- range event detection while the digital host sleeps. The averaging modes deliver on-demand, high-resolution measurements while offloading computations from the host processor. The self-timed device enable signal (DEV_EN) synchronizes AFE device power cycling to the ADC sampling instant, optimizing system power consumption while minimizing power-up settling error artifacts. The AD4052/AD4058 also supports power cycling the voltage reference and using the supply as the ADC reference voltage (V REF ) for additional power savings.

Device configuration and ADC data readback are supported via a robust, 4-wire serial peripheral interface (SPI) with cyclic redundancy check (CRC) supported for all data transfers. The AD4052/AD4058 are available in compact LFCSP and WLCSP packages and operates across a wide temperature range, making it ideal for a diverse set of applications.

APPLICATIONS

  • Battery-powered data acquisition
  • Vital signs monitoring
  • Biological and chemical analysis
  • Geologic and seismic sensing
  • Motion and robotics
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ADI 始终高度重视提供符合最高质量和可靠性水平的产品。我们通过将质量和可靠性检查纳入产品和工艺设计的各个范围以及制造过程来实现这一目标。出货产品的“零缺陷”始终是我们的目标。查看我们的 质量和可靠性计划和认证 以了解更多信息。

产品型号 引脚/封装图-中文版 文档 CAD 符号,脚注和 3D模型
AD4052BCBZ-RL7 CHIPS W/SOLDER BUMPS/WLCSP
  • HTML
  • Material Declaration external-link
  • HTML
  • Reliablity Data external-link
AD4052BCPZ-R2 LFCSP:LEADFRM CHIP SCALE
  • HTML
  • Material Declaration external-link
  • HTML
  • Reliablity Data external-link
AD4052BCPZ-RL7 LFCSP:LEADFRM CHIP SCALE
  • HTML
  • Material Declaration external-link
  • HTML
  • Reliablity Data external-link
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Mbed支持

正在寻找评估软件?您可以在这里找到

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部分模型 产品周期 描述

正线性稳压器(LDO) 3

推荐新设计使用

20 V、200 mA、低噪声、CMOS LDO线性稳压器

推荐新设计使用

20 V、200 m A低噪声CMOS LDO线性稳压器

量产

超低噪声、150 mA CMOS线性调节器

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评估套件 1

reference details image

EVAL-AD4052-ARDZ

Evaluating the AD4050/AD4052 Compact, Low Power, 12-Bit/16-Bit, 2 MSPS Easy Drive SAR ADCs

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工具及仿真模型 2

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文章来源于: analog.com 原文链接

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